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Thursday, September 14


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Room/Location

Virtual

Description

Cyber-physical real-time systems are information processing systems that require both functional as well as timing correctness and have interactions with the physical world. In many applications of cyber-physical systems, a sequence of tasks is necessary to perform a certain functionality. For example, from a sensor to an actuator, the first task reads the sensor value (cause), the second task processes the data, and the third task produces an output for the actuator (an effect is triggered). The data dependency between such tasks can be described by the data flow of a cause-effect chain. This education class provides the historical perspectives and the state-of-the-art analyses to safely bound the *end-to-end* timing properties of such cause-effect chains regarding the reaction time (how fast can a reaction be in the worst case) and the data age (how old is the data source of an actuation in the worst case). We will cover also examples on how to extend the results to deal with data flows in Robot Operating Systems (ROS) 2. This class provides a unique opportunity for those who are interested in applying results from classical real-time systems to deal with a new class of timing properties in distributed systems where *data freshness* plays an important role.


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Room/Location

Virtual

Description

3D stacking offers exciting new possibilities for compact, high-performance memory systems with high data access throughput. However, the resulting higher power densities lead to thermal hotspots that need careful system level management. Dynamic Thermal Management strategies need to be intelligently co-ordinated with voltage/frequency scaling and task mapping decisions to deliver the highest performance in the presence of thermal constraints. Advance knowledge of the nature of the processing, such as that in the neural network domain, leads to further improvements through application-specific customization of such decisions. In this ESWEEK Education Class, we discuss the foundations and recent developments in this fast-moving inter-disciplinary field involving innovations covering a wide engineering spectrum from packaging to system level design. The Education Class will also include a hands-on tutorial component involving the open-source CoMeT simulation platform which integrates performance simulators, thermal simulators, and high-level power/energy models, to enable system level studies.

Room/Location

Virtual

Description

Popular frameworks based on publish-and-subscribe, service-oriented architectures, and actor networks have simplified the development of parallel and distributed software. Most of these, however, are intrinsically nondeterministic. This tutorial will examine some of the risks that this introduces to applications, particularly cyber-physical applications. We will then introduce a polyglot coordination language called Lingua Franca (LF) that provides deterministic concurrency and real-time features. We will show that deterministic concurrency does not automatically imply a cost in performance. Finally, we will show how LF enables navigating the fundamental and unavoidable tradeoff between consistency and availability in distributed systems.

Room/Location

Virtual

Description

The deployment of Artificial Intelligence (AI) techniques at the edge has become prevalent. In this two-hour tutorial, we present some principles of designing an efficient and robust edge AI system from software, hardware, and the co-design perspectives. In particular, we will discuss: 1) efficient AI models, including deep neural network (DNN) model pruning, quantization, compression and architecture search, 2) efficient AI hardware, including AI accelerators and in-memory computing (IMC) designs; and 3) federated learning (FL) system designs by considering the challenges of data privacy and system heterogeneity.

Room/Location

Virtual

Description

As the computing landscape evolves, system designers continue to explore design methodologies that leverage increased levels of heterogeneity to push performance within the limited size, weight, power, and cost budgets. One such methodology is to build Domain-Specific System-on-Chips (DSSoCs) that promise increased productivity through the narrowed scope of their target application domain. We developed CEDR, an open-source, unified compilation and runtime framework for DSSoC architectures that allows applications, scheduling heuristics, and accelerators to be co-designed in a cohesive manner that maximizes system performance. This tutorial presents an overview of CEDR and its productive, API-based programming and deployment methodology. For this we will start with a baseline C/C++ application and walk through the steps of how developers use CEDR APIs to rapidly convert their applications for executing on a heterogeneous SoC. We will then walk through the fully automated compilation flow and deploy the application on two COTS-based SoCs: Nvidia Jetson Xavier GPU and Xilinx ZCU102. We will demonstrate the plug-and-play scheduling interfaces by way of training and integrating a new Imitation Learning (IL)-based heuristic into the runtime.

Room/Location

Virtual

Description

This education class will cover the motivators, intuitions, and fundaments of machine learning accelerator design. The class lecture will cover topics such as the basics of ML, the need for accelerators, and the different types of accelerators designs proposed. The class will cover the application of accelerators in image processing, NLP, and neuromorphic computing, and their role in training and sparsity. The class will conclude with a discussion of the relevance of accelerators and their drawbacks, and strategies to overcome these challenges.

Friday, September 15


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Room/Location

Virtual

Description

High-Level synthesis (HLS) is the process of converting specifications in high-level languages, such as C or C++, to designs in hardware description languages (HDLs), such as Verilog or VHDL, and is a necessary methodology to make productive use of reconfigurable devices such field-programmable gate arrays (FPGAs). HLS tools are very effective in extracting and optimizing applications leveraging instruction-level parallelism (ILP). Leveraging task-level parallelism (TLP) is very appealing to fully utilize the large area made available by modern devices. This tutorial will first provide an overview of the foundations of high-level synthesis and then delve into some advanced techniques for parallel specifications, focusing on some of the solutions targeted at memory intensive codes with irregular behaviors that we integrated in PandA-Bambu HLS, a state-of-the-art open-source HLS tool. We will finally provide an overview of the opportunities provided by novel compiler infrastructures such as MLIR for HLS.


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Room/Location

Virtual

Description

The Coarse-Grained Reconfigurable Array (CGRA) represents a class of spatial accelerators offering high performance, energy efficiency, and the flexibility to support an extensive range of application domains. While general-purpose processors deliver high performance and programmability, their energy efficiency remains low. Conversely, domain-specific hardware accelerators exhibit high performance and energy efficiency due to specialization but fall short in terms of programmability. CGRAs are software-defined hardware accelerators that bridge the gap between the two paradigms and deliver efficiencies comparable to custom accelerators while maintaining versatility to support diverse applications through generalization. A CGRA architecture comprises an array of processing elements connected via on-chip interconnect where both the processing elements and the interconnect can be reconfigured on a per cycle basis. The compiler instantiates a specialized accelerator for each application on the same CGRA silicon by generating the reconfiguration directives. We will present a comprehensive review of the CGRAs starting with the historical context, sketching the architectural landscape, and providing an overview of the compilation approaches.

Room/Location

Virtual

Description

In the development of an embedded computer vision system, there are many issues to consider, such as which hardware platform and algorithm to use, how to optimize the software with resource constraints and how to optimize multiple design objectives, and so on. This lecture presents a systematic design methodology that could be applied to the design of embedded computer vision systems. Based on the proposed methodology, we could win the first prize in LPIRC (Low-Power Image Recognition Challenge) 2017 and in track 2 of LPIRC 2018 using a NVIDIA Jetson TX2 board. Recently new hardware platforms have been developed that contain CNN (Convolutional Neural Network) hardware accelerators as well as GPU (Graphics Processing Units), among which NVIDIA Jetson AGX Xavier is a representative example. Since it is a heterogeneous system that contains multiple hardware accelerators, exploiting the computing power of those accelerators maximally becomes an important issue to consider in the proposed design methodology. I will present a novel technique to support multiple deep learning applications as well as other dataflow applications on such a heterogeneous multi-processor platform.

Room/Location

Virtual

Description

Various applications demand more and more powerful machine inference in resource-scarce distributed devices. To allow intelligent applications at ultra-low energy and low latency, one needs 1.) compact, yet efficient ML models; 2.) customized processors architectures for extreme edge ML. This has resulted in a wide variety of HW-algorithm co-optimization methods proposed in the SotA. This talk will zoom into model efficiency and architecture techniques for both hyper-dimensional as well as convolutional machine learning models, supported with practical examples and implementations.

Room/Location

Virtual

Description

Emerging AI applications such as ChatGPT, graph convolutional networks, and other deep neural networks require massive computational resources for training and inference. Contemporary computing platforms such as CPUs, GPUs, and TPUs are struggling to keep up with the demands of these AI applications. Optical computing represents an exciting new paradigm for light-speed acceleration of AI workloads. In this education class, I will cover the fundamentals of how optical computing works and discuss state-of-the-art developments in research and commercial prototyping for optical computing. I will describe approaches for optical device engineering, optical circuit enhancements, and architectural innovations to adapt optical computing to a variety of AI workloads. I will also discuss techniques for hardware/software co-design that can intelligently map and adapt AI software to improve performance and energy-efficiency on optical computing platforms.

Room/Location

Description

Presenters: Éricles Sousa, Felipe Augusto da Silva
The automotive industry is undergoing a rapid transformation driven by advancements in technology. Advanced driver assistance systems (ADAS), electric and autonomous vehicles, as well as connected cars are becoming the new normal, demanding more computing power, safety, reliability, security, and connectivity than ever before. This lecture aims to provide an overview of the following five must-have features of modern automotive SoCs and how they enable the development of next-generation automotive systems.

Room/Location

Virtual

Description

The complexity and high demand for real-time and energy-efficient computing for autonomous systems, such as cars, robots and drones, require novel domain-specific hardware/software solutions. Data from multiple sensors must be processed in parallel with a variety of signal/image processing algorithms. In addition, the autonomous systems must quickly adapt to changing situations at runtime, e.g., by switching the executed algorithm from navigation to object detection in robotics. To achieve high energy efficiency, this adaptation requires a change in both the signal/image processing algorithms and the underlying computational architecture for these specific algorithms. This feature can be provided by self-adaptive domain-specific computer architectures using reconfigurable hardware, where each component (software, processor, accelerator, communication infrastructure, memory) can be adapted at design- and runtime according to application demands.
This talk will present concepts and realizations for such an approach including hardware architecture, design/programming methods and runtime management. The importance of such an approach will be demonstrated using several research projects with robotics and drone applications.

Saturday, September 16

Sunday, September 17


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Room/Location

A0.18

Description

This tutorial will briefly introduce the heterogeneous Versal Adaptive Compute Acceleration Platform (ACAP). We will primarily focus on the Adaptable Intelligent Engine (AIE), a new type of compute element in the latest AMD technology. The AI Engines are a tiled array of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) processing elements that provide high compute density.

In this tutorial we will describe the AI Engine tile and array architecture as well as the different connectivity methods. We will also have an introduction to AI Engine programming which consists of a Data Flow Graph Specification written in C++ and the kernel description, written either in C or C++.

The application can be compiled and executed using the AI Engine tool chain, which is part of the Vitis Unified Software platform that enables the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto heterogeneous CPU-FPGA-ACAP systems.


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Room/Location

A0.14

Description

This hands-on class will have attendees develop an inferencing accelerator using High-Level Synthesis (HLS). The CNN used as an example in the class will be the MNIST handwritten character recognition algorithm, but the techniques used will be applicable to far more sophisticated neural networks. Students will start with a Keras Python implementation of the CNN and migrate it to a fully synthesizable Verilog RTL implementation. The class will cover how to trade off power consumption, performance, and network accuracy as the bespoke accelerator is designed. It will look at numeric representations and quantization, and their relationship to performance and area. Finally, it will detail verification strategies for the synthesized Verilog and intermediate representations. Participants will gain an understanding of how to create a bespoke inferencing accelerator and the benefits that it can bring to an embedded system.

Room/Location

A1.19

Description

Model checking can be a valuable addition to industry-standard approaches to perform quantitative and qualitative analysis of circuits at the transistor level. The device models are simple yet powerful enough to capture essential electrical characteristics. With its unique approach to formally specify the experimental setup and query quantitative measures, model checking provides you definitive answers to questions about energy consumption, power dissipation and delay properties. With the advent of reconfigurable transistors, systematic investigation and comparison becomes even more important, as reconfigurable logic gates come in different implementations with varying trade-offs. This tutorial will give you a hands-on introduction into the possibilities of investigating logic circuits that use reconfigurable transistors. You will both, design a single circuit graphically, and synthesize a whole family of reconfigurable circuits automatically from a Boolean function. You then analyze their netlist specifications with respect to various properties.

Room/Location

A1.19

Description

This interactive tutorial will describe state-of-the-art methods for formally verifying neural networks and their usage within safety-critical cyberphysical systems (CPS). The tutorial will begin with a lecture on this emerging research area, followed by demos of these methods implemented in software tools, specifically the Neural Network Verification (NNV) tool. Examples will include systems from aerospace, automotive, and beyond. In this tutorial, we will demonstrate NNV capabilities through a collection of safety and robustness verification tasks, which involve the reachable set computation of feedforward, convolutional, semantic segmentation, and recurrent neural networks, as well as neural ordinary differential equations and neural network control systems. The tutorial will be interactive, and as NNV is publicly available, participants can follow along as desired. Publications on NNV have participated in several prior repeatability/artifact evaluations at top conferences such as CAV, with passing results for multiple publications, which illustrates the feasibility of this interactive demonstration plan. Further. NNV is already available for in-browser execution through platforms like CodeOcean, and we plan to organize the interactive tutorial aspects around this or similar (Jupyter-like) in-browser demonstrations.

Room/Location

A0.19

Description

From datacenters to embedded devices, modern realtime workloads are demanding exceptional computational capacity from state-of-the-art systems, while satisfying energy constraints, real-time deadlines, mixed criticality workloads, and satisfactory QoS. In response, researchers have proposed resource management policies to maximize system utilization and efficiency, e.g., power managers, dynamic frequency and voltage scaling governors, task mappers and schedulers, offloading orchestrators, etc. Policies can utilize techniques from various algorithmic domains, e.g., game theory, control theory, and machine learning. In this tutorial, we give an overview and demonstration of MARS (Middleware for Adaptive and Reflective Systems), a cross-layer and multi-platform framework developed by Dutt Research Group at UC Irvine that allows system designers to easily create resource managers by composing system models and resource management policies in a flexible and coordinated manner. MARS consists of a generic user-level sensing/actuation interface that allows for portable policy design, and a reflective system model used to coordinate multiple policies. We demonstrate MARS’ ability to deploy a low-overhead realtime resource manager through a dynamic voltage and frequency scaling (DVFS) policy example which can run on any Linux-based HMP computing platform. We also demonstrate MARS’ ability to transparently collect, store, and analyze realtime application behavior at scale through an architectural monitor for (1) a rack server executing inference services and (2) an embedded developer board executing autonomous driving tasks.

The tutorial will start with an introductory session giving an overview of the technical content covered in the tutorial: realtime telemetry, system modeling, resource management policies. A guest speaker from Meta/Facebook Capacity Engineering and Analysis Group (e.g., Parth Malani or David Cisneros, to be confirmed) will present the challenges of telemetry and modeling at scale that the industry is currently facing. The first session will cover the design and implementation of MARS 1.0 for realtime monitoring and control of embedded systems-on-chip. Use cases and results will be presented. The second session will cover the design and implementation of MARS 2.0, and its ability to portably monitor and control distributed systems at scale. A demonstration of MARS 2.0 will be presented, including how to set up scalable monitoring telemetry, visualize live monitor data, and deploy an application-level runtime policy for two use cases: (1) a rack server executing inference services and (2) an embedded developer board executing autonomous driving tasks.

Room/Location

A0.19

Description

Breakthroughs in deep learning consistently drive innovation. However, DNNs tend to overwhelm conventional computing systems. Hyperdimensional Computing (HDC) is rapidly gaining prominence as a potent method for rapid learning from a relatively small amount of data. It also holds the promise of offering energy-efficient lightweight computation. This tutorial will provide a comprehensive overview of the major shortcomings of existing von Neumann architectures and the growing need for innovative designs that fundamentally reduce memory latency and energy consumption by enabling data processing within the memory itself. Additionally, the tutorial will delve into the immense potential of beyond-von Neumann architectures, which utilize both emerging beyond-CMOS devices like Ferroelectric Field-Effect Transistors (FeFET) and conventional CMOS devices. The tutorial will last for 3 hours and will adopt a hands-on approach. It will begin with a comprehensive overview of brain-inspired hyperdimensional computing and its remarkable synergy with beyond von Neumann architectures, such as Compute-in-Memory (CiM)-based hardware acceleration. Participants will gain in-depth practical experience in effectively applying HDC algorithms for various machine learning tasks. The hands-on tutorial will cover HDC training and HDC inference for different classification tasks.

Room/Location

A0.13

Room/Location

A0.13

Room/Location

A0.13

Room/Location

A0.13

Room/Location

Description

The Sunday reception will be from 18:00 – 20:00 in the ESWEEK Lunch & Coffee Area in Building A. It’ll include mixed finger food (both veggie and non-veggie) and beverages (both with or without alcohol).

Monday, September 18


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Room/Location

H Audimax 1


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Room/Location

H Audimax 1

Description

Computing is on the brink of a new immersive era. Recent innovations in virtual/augmented/mixed reality (extended reality or XR) show the potential for a new immersive modality of computing that will transform most human activities and change how we design, program, and use computers. There is, however, an orders of magnitude gap between the power/performance/quality-of-experience attributes of current and desirable immersive systems. Bridging this gap requires an inter-disciplinary research agenda that spans end-user embedded devices, edge, and cloud, is based on hardware-software-application co-design, and is driven by end-to-end human-perceived quality of experience.

The ILLIXR (Illinois Extended Reality) project has developed an open source end-to-end XR system to enable such a research agenda. ILLIXR is being used in academia and industry to quantify the research challenges for desirable immersive experiences and provide solutions to address these challenges. To further push the interdisciplinary frontier for immersive computing, we recently established the IMMERSE center at Illinois to bring together research, education, and infrastructure activities in immersive technologies, applications, and human factors. This talk will give an overview of IMMERSE and a deeper dive into the ILLIXR project, including the ILLIXR infrastructure, its use to identify XR systems research challenges, and recent solutions to address several of these challenges (e.g., using co-designed device/edge/cloud, algorithmic frequency adaptation, and approximate computing based techniques). We will conclude with the large number of open issues that remain, providing a fertile ground for participation by the embedded systems community.

Room/Location

A0.13

Description

Chair: Jeronimo Castrillon
This session covers papers addressing co-design for machine learning workloads. The regular papers focus on task mapping for deep learning workloads, hardware-aware neural architecture search, and graph neural network accelerators. The WiPs address co-design for energy-efficient and scalable convolutional neural networks.

Papers/Talks
  • 10:30-10:55

  • Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs

    Best paper candidate.
    Authors: Tzung-Han Juang, Christof Schlaak and Christophe Dubach
  • 10:56-11:21

  • MaGNAS: A Mapping-Aware Graph Neural Architectural Search Framework for Heterogeneous MPSoC Deployment

    Authors: Mohanad Odema, Halima Bouzidi*, Hamza Ouarnoughi, Smail Niar and Mohammad Al Faruque
  • 11:22-11:47

  • GHOST: A Graph Neural Network Accelerator using Silicon Photonics

    Authors: Salma Afifi, Febin Sunny, Amin Shafiee, Mahdi Nikdast and Sudeep Pasricha
  • 11:48-11:53

  • WiP: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs

    Authors: Xingyu Xu, Qingwen Wei, Yang Zhang, Hao Cai and Bo Liu
  • 11:54-11:59

  • WiP: QRCNN: Scalable CNNs

    Authors: Dara Nagaraju and Nitin Chandrachoodan

Room/Location

H0.01+H0.02

Description

Session Chair: Prof. Aviral Shrivastava, Arizona State University
This session presents three Regular Journal Track papers and one Late-Breaking Results paper. The first paper introduces a HW/SW co-design methodology to integrate per-layer quantization and inter-layer scaling along with a lightweight hardware support for overflow-free computation of dot-vector operations. The second paper presents a technique to avoid FP processor in crossbars by reusing bitshifts for multiplying scaling factors, in conjunction with a method to eliminate the hardware units for data aligning through kernel-group pruning and crossbar pruning. The third paper proposes an in-memory Bayesian approximation technique with a multilevel spintronic bitcell design and a Bayesian network for efficient sampling to significantly reduce the memory overhead and energy consumption. The LB paper introduces a method for training a Transformer architecture for resource-constrained scenarios and memory-efficient inference.

Papers/Talks
  • 10:30-10:55

  • Overflow-free compute memories for edge AI acceleration

    Best paper candidate.
    Authors: Flavio Ponzina, Marco Rios, Alexandre Levisse, Giovanni Ansaloni and David Atienza
  • 10:56-11:21

  • CRIMP: Compact & Reliable DNNs Inference for In-Memory Processing via Crossbar-Aligned Compression and Non-ideality Adaptation

    Authors: Shuo Huai, Hao Kong, Xiangzhong Luo, Shiqing Li, Ravi Subramaniam, Christian Makaya, Qian Lin and Weichen Liu
  • 11:22-11:47

  • SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures

    Authors: Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel and Mehdi Tahoori
  • 11:48-11:53

  • LB: Differentiable Slimming for Memory-Efficient Transformers

    Authors: Nikolay Penkov, Konstantinos Balaskas, Martin Rapp and Joerg Henkel

Room/Location

H0.16

Description

Session Chair: Arne Hamann
This session addresses safety-critical systems design and in particular
correct-by construction languages compilation. The regular papers focus
on formal proved compilation approaches either with theorem prover or
SAT/SMT, two of them for Lustre synchronous language programs and the
3rd for Lingua Franca programs. The WiPs also address compilation
problems either for LLVM or for an RTL language close to OCaml.

Papers/Talks
  • 10:30-10:55

  • 117 Towards Building Verifiable CPS using Lingua Franca.

    Shaokai Lin, Yatin A. Manerkar, Marten Lohstroh, Elizabeth Polgreen, Sheng-Jung Yu, Chadlia Jerad, Edward Lee and Sanjit A. Seshia
  • 10:56-11:21

  • 87 Equation-Directed Axiomatization of Lustre Semantics to Enable Optimized Code Validation

    Best paper candidate. Lélio Brun, Christophe Garion, Pierre-loic Garoche and Xavier Thirioux
  • 11:22-11:47

  • 11 Verified Compilation of Synchronous Dataflow with State Machines

    Best paper candidate — Timothy Bourke, Basile Pesin and Marc Pouzet
  • 11:48-11:53

  • 144 WiP: Searching Optimal Compiler Optimization Passes Sequence for Reducing Runtime Memory Profile using Ensemble Reinforcement Learning

    Juneseo Chang and Daejin Park
  • 11:54-11:59

  • 153 WiP: Mixing computation and interaction on FPGA

    Loic Sylvestre, Emmanuel Chailloux and Jocelyn Sérot

Room/Location

H0.03

Description

Machine learning (ML) has become increasingly popular in recent years, due to its ability to make predictions or decisions based on the data. One trend in the field of machine learning for embedded systems is the development of more lightweight and efficient algorithms that can run on devices with limited computational resources. The Tiny and Fair ML Design Contest at ESWEEK 2023 features two exciting tracks: Segmentation and Classification, requiring the participants to implement ML algorithm on edge devices. The contest will run for several months and be open to multi-person teams world-wide. The winning teams will be announced and awarded at the ESWEEK. Embedded Systems Software Competition (ESSC) at ESWEEK brings together software and tools used for embedded systems and design automation research. Research in embedded systems and internet of things (IoT) is often supported by novel software/tools that are used to simulate, emulate, or validate research artifacts. The software systems are typically not described in depth as part of research articles but are equally important to make research reproducible and for follow up work. This competition aims to promote novel tools and software for benefit of the broader community.

Room/Location

Room/Location

A0.13

Description

Chair: Sudeep Pasricha
This session covers papers addressing high-performance, energy-efficient, and secure edge computing. The regular papers focus on topics including energy-efficient personalization, light-weight malware detectors, and missing data imputation for wearable applications. The WiPs address the integrity attacks on CNNs executed on shared platforms and efficient deployment of DNNs on heterogeneous platforms.

Papers/Talks
  • 13:30-13:55

  • Energy-efficient Personalized Federated Search with Graph for Edge Computing

    Authors: Zhao Yang and Qingshuang Sun
  • 13:56-14:21

  • ViT4Mal: Lightweight Vision Transformer for Malware Detection on Edge Devices

    Authors: Akshara Ravi, Vivek Chaturvedi and Muhammad Shafique
  • 14:22-14:47

  • CIM: A Novel Clustering-based Energy-Efficient Data Imputation Method for Human Activity Recognition

    Authors: Dina Hussein and Ganapati Bhat
  • 14:48-14:53

  • WiP: Towards Evaluating CNNs Against Integrity Attacks on Multi-tenant Computation

    Authors: Xiangru Chen, Dipal Halder, Kazi Mejbaul Islam and Sandip Ray
  • 14:54-14:59

  • WiP: Automatic DNN Deployment on Heterogeneous Platforms: the GAP9 Case Study

    Authors: Luka Macan, Alessio Burrello, Luca Benini and Francesco Conti

Room/Location

H0.01+H0.02

Description

Session Chair: Soonhoi Ha, Seoul National University
This session presents three Regular Journal Track papers and one Late-Breaking Results paper. The first paper presents a Network-on-Interposer for CNN inference that enables efficient task mapping and inter-chiplet data exchange for increased performance and energy efficiency. The second paper introduces an approach run-time dynamic reconfiguration of inference engines and explores the interplay between data refetch and reuse. The third paper presents a photonic neural accelerator for backpropagation to enable high-performance training, where the key is to accelerate key operations like multiplication, accumulation, and subtraction used on gradient computations. The LB paper introduces a framework for dynamic fusion of multimodal ML inference using weight updates based on run-time parameters of different modalities.

Papers/Talks
  • 13:30-13:55

  • Florets for Chiplets: Data Flow-aware High-Performance and Energy-efficient Network-on-Interposer for CNN Inference Tasks

    Best paper candidate.
    Authors: Harsh Sharma, Lukas Pfromm, Rasit Onur Topaloglu, Jana Doppa, Umit Ogras, Ananth Kalyanaraman and Partha Pratim Pande
  • 13:56-14:21

  • Keep in Balance: Runtime-reconfigurable Intermittent Deep Inference

    Best paper candidate.
    Authors: Chih-Hsuan Yen, Hashan Mendis, Tei-Wei Kuo and Pi-Cheng Hsiu
  • 14:22-14:47

  • STADIA: Photonic Stochastic Gradient Descent for Neural Network Accelerators

    Authors: Chengpeng Xia, Yawen Chen, Haibo Zhang and Jigang Wu
  • 14:48-14:53

  • LB: DynaFuse: Dynamic Fusion for Resource Efficient Multi-modal Machine Learning Inference

    Authors: Hamidreza Alikhani Koshkak, Anil Kanduri, Pasi Liljeberg, Amir M. Rahmani and Nikil Dutt

Room/Location

Description

Session chair: Kasim Sinan Yildirim
This session focuses on two important aspects of mobile and
resource-constrained systems: improving the performance of interactive
applications and on-device learning.
Methods to improve the efficiency of kernel page reclaiming, improve the
scheduling of kernel and framework services, and reduce the rendering
redundancy are presented by three papers. The other two papers present
optimized methods to enable efficient on-device learning on devices
with limited memory resources.

Papers/Talks
  • 13:30-13:55

  • 47 DaCapo: An On-Device Learning Scheme for Memory-Constrained Embedded Systems

    Osama Khan, Gwanjong Park and Euiseong Seo
  • 13:56-14:21

  • 57 iAware: Interaction Aware Task Scheduling for Reducing Resource Contention in Mobile Systems

    Yongchun Zheng, Changlong Li, Yi Xiong, Weihong Liu, Cheng ji, Zongwei Zhu and Lichen Yu
  • 14:22-14:47

  • 25 Rectifying Skewed Kernel Page Reclamation in Mobile Devices for Improving User-Perceivable Latency

    Best paper candidate — Yi-Quan Chou, Lin-Wei Shen and Li-Pin Chang
  • 14:48-14:53

  • LB – Efficient Partial Weight Update Techniques for Lightweight On-Device Learning on Tiny Flash-Embedded MCUs

    Daejin Park and Jisu Kwon
  • 14:54-14:59

  • 140 WiP: CLERR: A High-performance Cross-layer Method for Eliminating Rendering Redundancy in Android

    shixiong Huang, nanxuan Ye, gao Xing, ziyang Kang, guilin Li and zhijun Li

Room/Location

H0.03

Description

Embedded Systems Software Competition (ESSC) at ESWEEK brings together software and tools used for embedded systems and design automation research. Research in embedded systems and internet of things (IoT) is often supported by novel software/tools that are used to simulate, emulate, or validate research artifacts. The software systems are typically not described in depth as part of research articles but are equally important to make research reproducible and for follow up work. This competition aims to promote novel tools and software for benefit of the broader community. ACM SIGBED SRC is the main student research competition in the real-time, embedded, and cyber-physical systems communities. The respective champions of the Undergraduate Category and the Graduate Category will represent SIGBED and compete against other SIGs in the ACM Grand Finals. In this final round, each participant has 8 minutes to present his/her original research work, followed by 4 minutes of Q&A.

Room/Location

Room/Location

Description

Chair: Joerg Henkel, Karlsruhe Institute of Technology
The emergence of novel non-volatile memory (NVM) technology marks a turning point in the design of intermittently-powered embedded systems. NVM offers the opportunity to provide persistent data structures which enable the system to maintain its state and data even in the presence of power shortages. NVM offer also the potential for more efficient embedded computing while carrying new challenges like wear and tear while key memory parameters like read/write access times vastly vary. This provides new trade-offs for customization in embedded systems design and for novel embedded architectures in general. In effect, the entire computing stack from programming and OS, through embedded systems architectures as well as micro-architectures are affected when NVM memories are deployed in an embedded system.

The goal of this special session is to demonstrate the new opportunities in embedded architectures with NVM memories and how in particular embedded machine learning applications can profit. The team of this ESWeek special session proposal offers a wide expertise ranging from compiling techniques

through embedded architectures and NVM technologies and consists of researchers from five institutions from Taiwan and Germany.

Papers/Talks
  • 15:30-15:55

  • Embedded Systems with Nonvolatile Main Memories – Programming for persistence and memory
    access time trade-offs

    by Jörg Henkel, Jürgen Teich, Stefan Wildermann, Lokesh Siddhu and Lars Bauer (KIT Karlsruhe and FAU Erlangen)
  • 15:56-16:21

  • Architecture to compiler co-optimization for computation in resistive non-volatile memories

    by Mehdi Tahoori, Mahta Mayahinia, Asif Ali Khan, Jeronimo Castrillon (KIT Karlsruhe and TU Dresden)
  • 16:22-16:47

  • Memory-Centric Machine Learning

    by Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng (TU Dortmund,
    University of Twente and NTU Taiwan)
  • 16:48-16:53

  • Prospects of Memory-Centric Computing on Flash Memories

    by Keh-Chung (KC) Wang, Chief Scientist, Macronix

Room/Location

H0.01+H0.02

Description

Session Chair: Dr. Lars Bauer, Karlsruhe Institute of Technology
This session presents three Regular Journal Track papers and two Work-in-Progress papers. The first paper introduces a self-sustained CPS with dynamic optimization for accuracy of wildfire detection and sensor active time, while leveraging the reinforcement learning to train the control policy. The second paper studies the tradeoffs between different factors for exploring the design space of light source activation pulse for optical sensing in wearables. The third paper presents an embedded ML framework for robust indoor localization and federated learning considering heterogeneous devices and data privacy, while leveraging domain-specific selective weight adaptations. The fourth paper presents a WiP that develops an efficient gait trajectory prediction model using K-means, DTW distance matrix, and weight template matching under soft constraints. The final paper of the session is a WiP that introduces a self-supervised transformer-based model to learn efficient representations of neural architectures, while being adaptive to different performance metrics.

Papers/Talks
  • 15:30-15:55

  • A Self-Sustained CPS Design for Reliable Wildfire Monitoring

    Authors: Yigit Tuncel, Toygun Basaklar, Dina Carpenter Graffy and Umit Ogras
  • 15:56-16:21

  • BASS: Safe Deep Tissue Optical Sensing for Wearable Embedded Systems

    Authors: Kourosh Vali, Ata Vafi, Begum Kasap and Soheil Ghiasi
  • 16:22-16:47

  • FedHIL: Heterogeneity Resilient Federated Learning for Robust Indoor Localization with Mobile Devices

    Authors: Danish Gufran and Sudeep Pasricha
  • 16:48-16:53

  • WiP: Efficient Gait Trajectory Prediction Method Based on Soft Constraint Weighted Template Matching

    Authors: Xing Liu, Yifan Liu and Xingjun Wang
  • 16:54-16:59

  • WiP: NAPMAE: Generalized Data-Efficient Neural Architecture Predictor with Masked Autoencoder

    Authors: Qiaochu Liang, Lei Gong, Chao Wang, Xuehai Zhou and Xi Li

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H0.16

Description

This session presents some strategies of using embedded networks of
safety-critical systems to provide formal guarantees. Two regular papers
address wired networks based on Ethernet by either reducing the latency
of sensors messages or by being robust against Byzantine failures thanks
to redundant topology. The 3rd paper focuses on 5G messages between
autonomous cars and proposes to improve the average safety. The WiP
papers address mixed-criticality handling on embedded networks.

Papers/Talks
  • 15:30-15:55

  • 63 CrossTalk: Making Low-Latency Fault Tolerance Cheap by Exploiting Redundant Networks

    Andrew Loveless, Linh Thi Xuan Phan, Lisa Erickson, Ronald Dreslinski and Baris Kasikci
  • 15:56-16:21

  • 15 Improving worst-case TSN communication times of large sensor data samples by exploiting synchronization

    Jonas Peeck and Rolf Ernst
  • 16:22-16:47

  • 109 B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles

    Matthew Szeto, Edward Andert, Aviral Shrivastava, Martin Reisslein, Chung-Wei Lin and Christ D. Richmond
  • 16:48-16:53

  • 136 WiP: Efficient TSN network interface handling in a mixed criticality system

    Romain Rollet and Christophe Mangin
  • 16:54-16:59

  • 139 WiP: Flexible bus arbitration in mixed criticality systems

    Vlad Radulescu, Albert Cheng and Stefan Andrei

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H0.03

Description

ACM SIGBED SRC is the main student research competition in the real-time, embedded, and cyber-physical systems communities. The respective champions of the Undergraduate Category and the Graduate Category will represent SIGBED and compete against other SIGs in the ACM Grand Finals. In this final round, each participant has 8 minutes to present his/her original research work, followed by 4 minutes of Q&A.

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Room/Location

A0.18.1 and A0.19

Tuesday, September 19


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H Audimax 1


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H Audimax 1

Description

The last few years have witnessed a strong evolution in quantum computing, making them move from research labs to data centers and easily accessible via the cloud. In this presentation I will provide an overview about our recent progress of our quantum systems based on superconducting quantum processors including processor size, speed, and quality. Integrating new technologies such as advanced packaging, high-density control signal delivery, developing advanced qubit control electronics have already enabled scaling of superconducting quantum processors to 433-qubits. Combined with increases in quality and speed this has driven significant improvements in the performance of quantum computers. Moreover, the computational capabilities of today’s quantum hardware can be extended by tight integration of quantum and classical resources using techniques like circuit knitting to accelerate the path towards quantum advantage. Developing approaches to connect individual quantum processors in various ways with classical as well as quantum communication links enables a modular approach to further scale quantum systems. The discussion of our Quantum Development Roadmap will illustrate the path to continuously increasing performance, capabilities, and value and finally the path towards quantum advantage will be highlighted.

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A0.13

Description

Chair: Mohammad A Al Faruque
This session covers papers on security of embedded systems for safety-critical and ML applications. The regular papers focus on topics including security-aware scheduling, design of safety-critical systems, and remote attestation. The LB papers address automated classification of attacks and rowhammer attacks.

Papers/Talks
  • 10:30-10:55

  • Protection Window Based Security-Aware Scheduling against Schedule-Based Attacks

    Best paper candidate.
    Authors: Jiankang Ren, Chunxiao Liu, Chi Lin, Ran Bi, Simeng Li, Zheng Wang, Yicheng Qian, Zhichao Zhao and Guozhen Tan
  • 10:56-11:21

  • Predictable GPU Wavefront Splitting for Safety-Critical Systems

    Authors: Artem Klashtorny, Zhuanhao Wu, Anirudh Mohan Kaushik and Hiren Patel
  • 11:22-11:47

  • PReFeR: Physically Related Function based Remote Attestation Protocol

    Authors: Anupam Mondal, Shreya Gangopadhyay, Durba Chatterjee, Harishma Boyapally and Debdeep Mukhopadhyay
  • 11:48-11:53

  • LB: LOCoCAT: Low-Overhead Classification of CAN bus Attack Types

    Authors: Caio Batista de Melo and Nikil Dutt
  • 11:54-11:59

  • LB: Flipping Bits Like a Pro: Precise Rowhammering on Embedded Devices

    Authors: Anandpreet Kaur, Pravin Srivastav and Dr. Bibhas Ghoshal

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H0.01+H0.02

Description

Session Chair: Prof. Sudeep Pasricha, Colorado State University
This session presents three Regular Journal Track papers and two Late-Breaking Results papers. The first paper introduces a multi-dimensional tree to improve the space and write efficiency for multi-dimensional point data on persistent memories. The second paper presents a detailed analysis flash-based memory swapping followed by an optimization framework with efficient I/O scheduling and I/O pattern reshaping to improve the I/O efficiency of memory swapping operations in flash memories deployed in mobile devices. The third paper introduces a request and response arbitration policy for shared caches to improve the overall system performance. The fourth paper provides late-breaking results on implementing an FPGA-based emulation platform for evaluating NVMs coupled with RISC-V cores. The last paper of the session introduces late-breaking results on CNN workload characterization for different tiny-YOLO versions on CPU-GPU embedded platforms while studying different DVFS governor policies for improved energy-delay product.

Papers/Talks
  • 10:30-10:55

  • WARM-tree: Making Quadtrees Write-efficient and Space-economic on Persistent Memories

    Authors: Shin-Ting Wu, Liang-Chi Chen, Po-Chun Huang, Yuan-Hao Chang, Chien-Chung Ho and Wei-Kuan Shih
  • 10:56-11:21

  • IOSR: Improving I/O Efficiency for Memory Swapping on Mobile Devices Via Scheduling and Reshaping

    Authors: Wentong Li, Liang Shi, Hang Li, Changlong Li and Edwin Hsing-Mean Sha
  • 11:22-11:47

  • CABARRE: Request Response Arbitration for Shared Cache Management

    Authors: Garima Modi, Aritra Bagchi, Neetu Jindal, Ayan Mandal and Preeti Ranjan Panda
  • 11:48-11:53

  • LB: NvMISC: Towards an FPGA-based Emulation Platform for RISC-V and Non-volatile Memories

    Authors: Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo and Akash Kumar
  • 11:54-11:59

  • LB: CNN Workloads Characterization and Integrated CPU-GPU DVFS Governors on Embedded Systems

    Authors: Meruyert Karzhaubayeva, Aidar Amangeldi and Jurn-Gyu Park

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H0.16

Description

Session chair: Timothy Bourke
This session presents new methods to analyze and optimize cause-effect
task chains in real-time systems, either investigating probabilistic
timing guarantees or optimizing the number of jobs to execute to
preserve a given semantic. Another work explores different methods to
realize preemptions in real-time systems that use multi-phase execution
models to manage the application data.
The session also includes a work that extends the notions of consistency
and availability in the context of cyber-physical systems, coping with
the physical state of the system and delays in actuation.

Papers/Talks
  • 10:30-10:55

  • 101 Methods to Realize Preemption in Phased Execution Models

    Thilanka Thilakasiri and Matthias Becker
  • 10:56-11:21

  • 14 Consistency vs. Availability in Distributed Cyber-Physical Systems

    Edward Lee, Ravi Akella, Soroush Bateni, Shaokai Lin, Marten Lohstroh and Christian Menard
  • 11:22-11:47

  • 51 Probabilistic Reaction Time Analysis

    Mario Günzel, Niklas Ueter, Kuan-Hsun Chen, Georg von der Brüggen and Jian-Jia Chen
  • 11:48-11:53

  • 152 LB: External Timed I/O Semantics Preserving Utilization Optimization for LET-based Effect Chain

    Bo Zhang, Caixu Zhao and Xi Li

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Description

Organizer: Prof. Paul Pop, Technical University of Denmark,
Co-Organizer: Prof. Martin Törngren, Royal Institute of Technology, Sweden

The drive towards a sustainable future has digital technologies at its core, providing a platform for greater efficiency and reduced environmental impact. This session explores the intersection of digital innovation with green initiatives, encompassing four interconnected talks. The first presentation offers a deep dive into the system-wide challenges and opportunities associated with the energy transition, emphasizing the importance of policy and its implications. Next, a focus on key digital technologies reveals their central role in the green transition, pinpointing research challenges and emerging opportunities. Delving into real-world applications, the third talk showcases use cases and lessons from efforts aimed at promoting sustainability through digitalization, highlighting the benefits of even simple digital tools and the challenges shaping the vision for a sustainable future. The last presentation, on multi-scale computing systems, stresses the need for energy-efficiency in data centers, edge AI, and IoT systems. Through this series, attendees will gain a comprehensive understanding of how digital technologies are shaping and supporting the green transition.

Papers/Talks
  • 10:30-10:53

  • Policy implications for the energy transition: Challenges and opportunities from a system perspective

    Speaker: Prof. Sonia Yeh (Chalmers University of Technology, Sweden; Vice director, Energy Area of Advance)
  • 10:53-11:15

  • Applying Green IoT digitalization for the Green Transition: Research challenges and opportunities

    Speaker: Prof. Paul Pop, Technical University of Denmark
  • 11:15-11:37

  • Digitalization in action: Use cases and lessons learned

    Dr. Christian Graulund (Danfoss Drives; Manager of Research and University Collaborations at Danfoss Drives
  • 11:37-12:00

  • Green ICT for energy-efficient data centers, edge AI and IoT systems

    Speaker: Dr. Xavier Eric Ouvrard, EPFL, EcoCloud

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Room/Location

A0.13

Description

Chair: T. Venkatesh
This session covers papers on design and optimization of memory systems at different levels of abstraction. The regular papers focus on topics including improving cache management in manycore and RAID systems, design of memory systems for recommendation engines, and design of efficient cache for SSD systems.

Papers/Talks
  • 13:30-13:55

  • ZPP: A Dynamic Technique to Eliminate Cache Pollution in NoC based MPSoCs

    Best paper candidate.
    Authors: Dipika Deb and John Jose
  • 13:56-14:21

  • EMS-I: An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation System Inference

    Authors: Yitu Wang, Shiyu Li, Qilin Zheng, Andrew Chang, Hai Li and Yiran Chen
  • 14:22-14:47

  • Proactive Stripe Reconstruction to Improve Cache Use Efficiency of SSD-Based RAID Systems

    Authors: zhibing sha, Jiaojiao Wu, Jun Li, Balazs Gerofi, Zhigang Cai and Jianwei Liao
  • 14:48-14:53

  • LB: Swift-CNN: Leveraging PCM Memory’s Fast Write Mode to Accelerate CNNs

    Authors: Lokesh Siddhu, Hassan Nassar, Lars Bauer, Christian Hakert, Nils Hölscher, Jian-Jia Chen and Joerg Henkel
  • 14:54-14:59

  • LB: No-Multiplication Deterministic Hyperdimensional Encoding for Resource-Constrained Devices

    Authors: Mehran Shoushtari Moghadam, Sercan Aygun and M. Hassan Najafi

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H0.01+H0.02

Description

Session Chair: Prof. Wanli Chang, Hunan University, China
This session presents three Regular Journal Track papers and two Late-Breaking Results papers. The first paper introduces new extensions to CoMeT, a 3D-chip simulator, with a learning-based thermal management using LPM power management knob for memory banks along with DVFS in a unified manner. The second paper presents an NVM-based arbiter PUF which is resilient to ML-based modeling. The third paper presents an automation framework for generating 3D-image registration pipelines with reconfigurable accelerator architectures. The fourth paper provides late-breaking results on studying the effects of run-time reconfiguration on PUFs that are used as FPGA=based reconfigurable accelerators. The last paper of the session introduces late-breaking results on hardware-software co-optimization of modeling and sizing of new logic gates with optimal latency for stochastic computing.

Papers/Talks
  • 13:30-13:55

  • Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power Regulation.

    Authors: Yixian Shen, Leo Schreuders, Anuj Pathania and Andy Pimentel
  • 13:56-14:21

  • ANV-PUF: Machine-Learning-Resilient NVM-Based Arbiter PUF

    Authors: Hassan Nassar, Lars Bauer and Joerg Henkel
  • 14:22-14:47

  • HEPHAESTUS: Codesigning and Automating 3D Image Registration on Reconfigurable Architectures

    Authors: Giuseppe Sorrentino, Marco Venere, Davide Conficconi, Eleonora D’Arnese and Marco D. Santambrogio
  • 14:48-14:53

  • LB: Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-based Accelerators

    Authors: Hassan Nassar, Lars Bauer and Joerg Henkel
  • 14:54-14:59

  • LB: Hardware-Software Co-optimization of Long-Latency Stochastic Computing

    Authors: Sercan Aygun, Lida Kouhalvandi, M. Hassan Najafi, Serdar Ozoguz and Ece Olcay Gunes

Room/Location

H0.16

Description

Session chair: Tulika Mitra
Optimization and design of embedded systems
This session focuses on the design of embedded systems. One regular
paper presents a functional semantic for SCADE and its associated
interpreter. The two other regular papers address machine learning-based
systems and strategies to minimise their footprint / execution times.
The LB paper proposes an optimized implementation of a path planner
algorithm. The WiP introduces a Rust-based kernel.

Papers/Talks
  • 13:30-13:55

  • 1 Sound Mixed Fixed-Point Quantization of Neural Networks

    Debasmita Lohar, Clothilde Jeangoudoux, Anastasia Volkova and Eva Darulova
  • 13:56-14:21

  • 93 A Constructive State-based Semantics and Interpreter for a Synchronous Data-flow Language with State machines

    Jean-Louis Colaço, Michael Mendler, Baptiste Pauget and Marc Pouzet
  • 14:22-14:47

  • 86 Optimal Synthesis of Robust IDK Classifier Cascades

    Sanjoy Baruah, Alan Burns and Robert Davis
  • 14:48-14:53

  • 150 LB: Optimized Local Path Planner implementation for GPU-accelerated embedded systems

    Filippo Muzzini, Nicola Capodieci, Federico Ramanzin and Paolo Burgio
  • 14:54-14:59

  • 142 WiP: Unishyper, A Reliable Rust-based Unikernel for Embedded Scenarios

    Keyang Hu, Lei Wang, Ce Mo and Bo Jiang

Room/Location

Description

Organizers: Siddharth Garg, NYU, Andreas Gerstlauer, UT Austin, Jiang Hu, Texas A&M University

Embedded systems are becoming increasingly complex, which has led to a productivity crisis in their design and verification. Although conventional design automation coupled with IP and platform reuse techniques have led to leaps in design productivity improvement, they face fundamental limits given that most design optimization and verification problems are NP hard and that reuse of pre-designed IP blocks and platforms inherently limits flexibility and optimality. At the same time, machine learning (ML) has recently made unprecedented advances and created phenomenal impact in various computing applications. In particular, application of ML techniques as a way to extract knowledge and learn from existing design, optimization and verification data has recently seen a lot of excitement and promise at lower physical and integrated circuit levels of abstraction. Using ML has the potential to similarly close the complexity gap in embedded system design, but corresponding ML-based approaches for embedded system optimization and verification at higher levels of abstraction are still at their infancy.

This special session will discuss the state of the art as well as opportunities and open challenges in applying ML methods for embedded system optimization and verification. The session consists of talks that discuss design and optimization at different levels of abstraction ranging from system-level modeling and optimization and high-level synthesis to RTL and micro-architecture design. The session brings together perspectives from both academia and industry, as well as communities not traditionally represented at ESWEEK.

Papers/Talks
  • 13:30-13:53

  • ML for System-Level Modeling and Design

    Speaker: Andreas Gerstlauer, UT Austin
  • 13:53-14:15

  • ML for High-Level Synthesis: Opportunities and Lessons

    Speaker: Zhiru Zhang, Cornell University
  • 14:15-14:37

  • Synthesis Prediction: Use Deep Learning to Expedite the Hardware Architecture
    and Design Process

    Speaker: Lisa Wu Wills, Duke University
  • 14:37-15:00

  • All AI Models are Wrong, Some are Useful: An Industry Perspective on the Role of Models and AI Tools in Embedded System Design

    Speaker: Prof. Wolfgang Ecker, Infineon & TU Munich

Room/Location

Room/Location

H Audimax 1

Description

The Global Semiconductor Renaissance and Embedded Computing: An Industry Perspective Panelists: Sankar Basu (NSF), Tobias Helbig (NXP), Heike Riel (IBM), Jin Yang (Intel)
Moderator: Marilyn Wolf (University of Nebraska – Lincoln)
This panel will discuss the impact of the global semiconductor renaissance on the practice of embedded computing. A range of technical and non-technical changes are sweeping the industry: new technologies; huge new investments in manufacturing; changes to supply chains. How will these technological and business changes affect the design of embedded computing systems?

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H0.03

Room/Location

Description

Social Events

Wednesday, September 20


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H Audimax 1


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H Audimax 1

Description

It is a long journey that data must travel: starting from the processes observed by an embedded system with the help of sensors, to the processing and communication of the corresponding data, and eventually to the extraction of knowledge and decision-making that could impact the observed processes. This sequence of stages remains largely unaffected by whether the involved processes are biological, physical, chemical, or of human origin. The corresponding distributed embedded systems are typically deeply integrated within their physical environments. Therefore, the associated challenges extend well beyond the typical considerations of real-time and predictable behavior that encompass a comprehensive understanding of the interplay between concurrent activities on shared resources. Instead, key scientific questions are closely linked to the need for adaptive and resilient functionality in the face of extreme resource constraints and fluctuating environmental conditions such as sensor degradation, data and concept drift, energy availability, and wireless connectivity. Consequently, it becomes necessary to consider embedded machine learning, information processing and communication across components and abstraction layers.

The focus will center on models and methods for designing resilient distributed embedded systems while discussing future challenges associated with embedded machine learning. However, the discussion extends beyond the scientific challenges encountered at each stage of the data journey. Can novel data-driven techniques and machine learning methods support us in gaining a better understanding of environmental processes, such as destructive processes in high alpine regions, and pave the way for reliable early warning systems? Additionally, we will explore examples relevant to the prediction of air pollution in highly contaminated areas and the subsequent derivation of embedded control mechanisms from such predictions.

Room/Location

A0.13

Description

Chair: Oliver Bringmann
This session covers papers on approximate computing in embedded systems. The regular papers focus on topics including design of approximate operators and data formats, improving design flexibility, and vector processing architectures. The LB papers address hyperdimensional encoding for resource-constrained devices, and approximate computing for solving traveling salesman problems.

Papers/Talks
  • 10:30-10:55

  • AxOTreeS: A Tree Search Approach to Synthesizing FPGA-based Approximate Operators

    Authors: Siva Satyendra Sahoo, Salim Ullah and Akash Kumar
  • 10:56-11:21

  • VADF: Versatile Approximate Data Formats for Energy-Efficient Computing

    Authors: Vishesh Mishra, Sparsh Mittal, Neelofar Hassan, Rekha Singhal and Urbi Chatterjee
  • 11:22-11:47

  • Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility

    Authors: Sosei Ikeda, Hiromitsu Awano and Takashi Sato
  • 11:48-11:53

  • LB: Vector-Based Dedicated Processor Architecture for Efficient Tracking in VSLAM Systems

    Authors: Li Dejian, Feng Xi, Shen Chongfei, Chen Qi, Yang Lixin, Qiu Sihai, Jin Xin and MENG LIU
  • 11:54-11:59

  • LB: An Approximate Parallel Annealing Ising Machine for Solving Traveling Salesman Problems

    Authors: Qichao Tao, Tingting Zhang and Jie Han

Room/Location

Description

Session Chair: Prof. Janardhan Rao Doppa, Washington State University
This session presents two Regular Journal Track papers, one Late-Breaking Results paper, and two Work-in-Progress papers.
The first paper introduces a locality-aware deduplication technique for Shingled magnetic recording devices that accounts for both the overheads of duplicate data writing and decision of writing duplicate data based on locality. The second paper proposes a new data management technique consider the file-system to improve write performance for interlaced magnetic recording, while considering the locality and time of update. The third paper presents late-breaking results on the energy-breakdown analysis in MAGIC operations and proposes a mapping technique to achieve accurate energy estimation through SPICE simulations. The fourth paper provides a work-in-progress on an instrumentation platform for NVMs. The last paper of the session introduces a work-in-progress on parallelizing a CPU model of a SystemC-TLM-2.0 based virtual platform, and compares the speedup for an octa-core ARM virtual platform.

Papers/Talks
  • 10:30-10:55

  • LaDy: Enabling Locality-aware Deduplication Technology on Shingled Magnetic Recording Drives

    Authors: Jung-Hsiu Chang and Tseng-Yi Chen
  • 10:56-11:21

  • FSIMR: File-system-aware Data Management for Interlaced Magnetic Recoding

    Authors: Yi-Han Lien, Yen-Ting Chen, Yuan-Hao Chang, Yu-Pei Liang and Wei-Kuan Shih
  • 11:22-11:27

  • LB: Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style

    Authors: Simranjeet Singh, Chandan Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin Patkar, Rolf Drechsler and Farhad Merchant
  • 11:48-11:53

  • WiP: A Universal Instrumentation Platform for Non-Volatile Memories

    Authors: Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph and Rainer Leupers
  • 11:54-11:59

  • WiP: A Generic Non-Intrusive Parallelization Approach for SystemC TLM-2.0-based Virtual Platforms

    Authors: Nils Bosbach, Rebecca Pelke, Niko Zurstraßen, Lukas Jünger, Jan Henrik Weinstock and Rainer Leupers

Room/Location

H0.16

Description

Session chair: Chih-Hong Cheng
This section mainly focuses on methods to automatically extract information from systems by observing their outputs and behavior.
The first paper presents a method for the automatic mining of hyperproperties of systems in the form of specifications based on temporal logic.
Another work presents an automated framework to identify the worst-case temporal interference suffered by programs on multi-core embedded platforms leveraging reinforcement learning.
Learning-enabled testing of systems is explored by the third paper, which proposes to learn Markov Decision Processes (MDP) to apply probabilistic model checking.
A work-in-progress paper finally presents a framework for enabling rapid prototyping in platforms with accelerators connected to micro-controllers.

Papers/Talks
  • 10:30-10:55

  • 135 Mining Hyperproperties using Temporal Logics

    Ezio Bartocci, Cristinel Mateis, Eleonora Nesterini and Dejan Nickovic
  • 10:56-11:21

  • 82 Kryptonite : Worst-Case Program Interference Estimation on Multi-Core Embedded Systems

    Nikhilesh Singh, Karthikeyan Renganathan, Chester Rebeiro, Jithin Jose and Ralph Mader
  • 11:22-11:47

  • 64 Probabilistic Black-Box Checking via Active MDP Learning

    Junya Shijubo, Masaki Waga and Kohei Suenaga
  • 11:48-11:53

  • 146 WiP: Micro-Accelerator-in-the-Loop Framework for MCU Integrated Accelerator Peripheral Fast Prototyping

    Jisu Kwon and Daejin Park

Room/Location

Room/Location

A0.13

Description

Chair: Partha Pande
This session covers papers on papers on the design optimization, runtime management, and security of system-on-chips. The regular papers focus on topics including including neuromorphic hardware design, runtime task scheduling, security of NoCs. The LB papers address the design of reconfigurable hardware for multi-precision multipliers and FPGA implementation of high-impact applications.

Papers/Talks
  • 13:30-13:55

  • SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip

    Authors: Judicael Clair, Guy Eichler and Luca Carloni
  • 13:56-14:21

  • DTRL: Decision Tree-based Multi-Objective Reinforcement Learning for Runtime Task Scheduling in Domain-Specific System-on-Chips

    Authors: Toygun Basaklar, A. Alper Goksoy, Anish Krishnakumar, Suat Gumussoy and Umit Ogras
  • 14:22-14:47

  • ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks

    Authors: Dipal Halder, Maneesh Merugu, and Sandip Ray
  • 14:48-14:53

  • LB: High Flexibility Designs of Quantized Runtime Reconfigurable Multi-precision Multipliers

    Authors: Yuhao Liu, Shubham Rai, Salim Ullah and Akash Kumar
  • 14:54-14:59

  • LB: FPGA Implementation of Modified SNOW 3G Stream Ciphers using Fast and Resource Efficient Substitution Box

    Authors: Sushree Sila P. Goswami and Gaurav Trivedi

Room/Location

Description

Organizer :Akash Kumar, TU Dresden

Side-Channel Attacks (SCAs) have been among the most prominent hardware threats that compromise the integrity and confidentiality of the circuits. These attacks exploit the information leaked from physical devices to retrieve the cryptographic keys stored in the secure chips or to circumvent the intellectual property (IP) protection scheme without a need for simulating powerful SAT attacks. As machine learning (ML) based techniques pave their way into hardware security in recent years, many deep-learning side-channel attacks have been proposed that provide new potent tools for attackers making SCAs even more threatening. Mitigating these powerful attacks requires a careful bottom-up multilayer defense strategy that starts from the silicon level and continues after the chip production by utilizing real-time monitoring and protection techniques.

This session includes four talks presenting various protection techniques against SCAs. The first talk discusses new circuit design paradigms based on emerging reconfigurable devices to protect circuits against SCAs. The second talk examines the EDA-level solutions that automatically provide SCA resiliency to the circuits. The third talk discusses the security risks posed by the side-channel analysis of edge devices and presents countermeasures to protect them against state-of-the-art SCAs. The fourth talk provides an industry perspective on emerging side-channel attacks on neural networks.

Papers/Talks
  • 13:30-13:53

  • Designing SCA-resilient Circuits with Emerging Reconfigurable Nanotechnologies

    Presenters: Nima Kavand, Armin Darjani, TU Dresden, Jens Trommer, Giulio Galderisi, Thomas Mikolajick,
    NamLab, Akash Kumar, TU Dresden
  • 13:53-14:15

  • Tools for Automated Generation of SCA-Protected Circuits

    Presenters: Amir Moradi, Ruhr University Bochum, Germany
  • 14:15-14:37

  • Obfuscation against Side-Channel Attacks in Edge Environments

    Presenters: Chongzhou Fang, Ning Miao, Han Wang, Sai Manoj, Houman Homayoun, UC Davis
  • 14:37-15:00

  • Industry Perspectives on Side-Channel Attacks and Defenses

    Presenters: Benjamin Hettwer, Robert Bosch Corporate Research

Room/Location

H0.16

Description

This section is mainly concerned with the analysis and design of control systems using innovative methods.
The first paper focuses on analyzing a control system in the presence of simultaneous failures
using Markov Jump Linear Systems.
The second paper presents a framework for synthesizing neural certificates to guarantee the safety of continuous dynamical systems using counterexample-guided learning.
The third paper shows how to use compressed representations of the system dynamics, based on neural networks, to reduce the memory requirements in the synthesis and deployment of controllers.
A WiP paper concludes the session: it addresses the integration of Web-Assembly modules into microservice-based software architectures.

Papers/Talks
  • 13:30-13:55

  • 55 Stochastic Analysis of Control Systems Subject to Communication and Computation Faults

    Nils Vreman and Martina Maggio
  • 13:56-14:21

  • 58 Formal Synthesis of Neural Barrier Certificates for Continuous Systems via Counterexample Guided Learning

    Hanrui Zhao, Niuniu Qi, Lydia Dehbi, xia zeng and Zhengfeng Yang
  • 14:22-14:47

  • 40 Neural Abstraction-Based Controller Synthesis and Deployment

    Rupak Majumdar, Mahmoud Salamati and Sadegh Soudjani
  • 14:48-14:53

  • 138 WiP: Integrating WebAssembly into Service Oriented Architectures for Edge Systems

    Marius Kreutzer, Maximilian Seidler, Victor Pazmino Betancourt and Juergen Becker

Room/Location

Room/Location

Description

Chair: Ganapati Bhat
This session covers papers on the co-design of ML acclerators. The regular papers focus on topics including task mapping for DNN workloads, hardware-aware neural architecture search, and adaptive inference for CNNs. The LB papers address efficient use of PCM memory for CNN acceleration and design of vector based processor architecture for VSLAM systems.

Papers/Talks
  • 15:30-15:55

  • Computationally Efficient DNN Mapping Search Heuristic using Deep Reinforcement Learning

    Authors: Suyash Bakshi and Lennart Johnsson
  • 15:56-16:21

  • DASS: Differentiable Architecture Search For Sparse neural networks

    Authors: Seyedhamidreza Mousavi, Mohammad Loni, Mina Alibeigi and Masoud Daneshtalab
  • 16:22-16:47

  • BitSET: Bit-Serial Early Termination for Computation Reduction in Convolutional Neural Networks

    Authors: Yunjie Pan, Jiecao Yu, Andrew Lukefahr, Reetuparna Das and Scott Mahlke

Room/Location

H0.16

Description

Computer Engineering Education, Embedded Computing, and the Semiconductor Renaissance
Panelists: Robert Dick (University of Michigan), Patrick Haspel (Synopsys), Muhammad Shafique (NYU), Marilyn Wolf (University of Nebraska – Lincoln), Wang Yu (Tsinghua University)
Moderator: Jan Madsen (Danish Technical University)
The global renaissance for the semiconductor industry emphasizes the need for the development of a large and capable workforce to meet the needs of the industry. This panel will explore opportunities for the embedded computing and computer engineering communities to contribute to semiconductor workforce development.

Thursday, September 21


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Room/Location

H0.01+H0.02

Description

MEMOCODE 1, 2, 3

Papers/Talks
  • 9:00 - 10:00

  • Keynote 1: Edward A. Lee

  • 10:30 - 12:30

  • Technical Session 1: Machine Learning

  • 13:30 - 15:00

  • Technical Session 2: Verification and Synthesis

  • 15:30 - 17:00

  • Technical Session 3: Specification and Verification


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Room/Location

H0.16

Description

NOCS 1, 2, 3

Papers/Talks
  • 9:00 - 10:00

  • Keynote 1

  • 10:30 - 12:30

  • Technical Session 1: High-Performance and Dynamic NoC Architectures

    This session comprises three papers dealing with latest advancements, challenges, and opportunities in high-performance and dynamic NoC architectures. The first paper describes an AXI4 compatible NoC implementation targeted for high-bandwidth applications. The second paper proposes an architecture for ad-hoc wireless networks where the authors describe a detail mechanism to enable random insertion and removal of nodes. The third paper presents a tutorial on processing in network-on-chip.
  • 13:30 - 15:00

  • Technical Session 2: NoCs for AI Acceleration and Interposer Systems

    This session presents papers that discuss breakthroughs in AI acceleration through NoCs. The first paper describes a spatial DNN inference accelerator geared towards the acceleration of CNNs. The second paper presents a novel architecture for in-memory computation-based DNN. This paper proposes an architecture that incorporates in-memory-computing chiplets, scratchpad memory, two network-on-packages, and network-on-chip to improve DNN training. The third paper presents compositional post-silicon validation of heterogeneous NoC-based SoCs.
  • 15:30 - 17:00

  • Technical Session 3: Routing and Deadlock Recovery in Interconnection Networks

    This session presents papers on routing and deadlock recovery in interconnection networks. The first paper presents a reinforcement learning framework with region-awareness and shared path experience for efficient routing in NoCs. The second paper proposes a new deadlock recovery mechanism that initially identifies a deadlock and then eliminates the cyclic dependence by reverse traversing a special packet in the deadlock loop. The third paper proposes a novel similarity-based technique that leverages the high degree of similarity available in the network.

Room/Location

Description

https://dot-pim-workshop.com/

Room/Location

Description

https://codai-workshop.com/

Room/Location

Description

Please check the agenda here http://2023.esweek.org/rsp-2023/

Room/Location

Description

The Thursday Symposium dinner will take place at the Restaurant Leuchtturm https://www.leuchtturm-harburg.de/ , Außenmühlendamm 2, 21077 Hamburg. It will start at 18:15 with a reception followed by a buffet at 19:15-23:15.

Friday, September 22


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Room/Location

H0.01+H0.02

Description

MEMOCODE 4, 5

Papers/Talks
  • 9:00 - 10:00

  • Keynote 2: Rolf Drechsler

  • 10:30 - 12:30

  • Technical Session 4: Hardware

  • 13:30 - 15:00

  • Technical Session 5: Models

  • 15:30 - 17:00

  • Closing Session


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Room/Location

H0.16

Description

NOCS 4, 5

Papers/Talks
  • 9:00 - 10:00

  • Keynote 2

  • 10:30 - 12:30

  • Technical Session 4: NoC Modeling, Optimization, and Verification

    This session deals with NoC modeling, optimization, and verification. The first paper presents a technique for analytical modeling for analysis of multiple-physical NoCs, which can often be seen in industrial settings. The second paper discusses hardware Trojan attack on on-chip packet compression. The third paper proposes an analytical model based on queuing theory to evaluate the latency of a hybrid interconnection that utilizes electrical and wireless NoCs for both intra- and inter-cluster communications.
  • 13:30 - 15:00

  • Special Session on New Architectures and Techniques for Edge Intelligence

    This special session focuses on new architectures and techniques in designing and implementing edge intelligence, and includes three contributions. The first paper discusses some hardware-aware design and optimization methods proposed for edge intelligence systems. The second paper presents hardware-software co-exploration for hyperdimensional computing based on network-on-chip architectures. The third paper discusses the development of a systematized framework to enable automated optical accelerator hardware architecture search.
  • 15:30 - 17:00

  • Panel and Best-Paper Award

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